Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoresistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low (logic “0” state) and high (logic “1” state) electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element.
There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. A reset current pulse will cause the final state to be parallel or logic “0”. A set current pulse, in the opposite polarity of reset current pulse, will cause the final state to be antiparallel or logic “1”. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element.
Spin-torque MRAM (ST-MRAM), also known as spin-transfer torque RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, increasing variability in MTJ resistance and sustaining relatively high switching currents through bit cell select devices in both current directions can limit the scalability of ST-MRAM. The write current is typically higher in one direction compared to the other, so the select device must be capable of passing the larger of the two currents. In addition, ST-MRAM switching current requirements increase as the write current pulse duration is reduced. Because of this, the smallest ST-MRAM bitcell approach may require relatively long switching times.
Data stored in memory is defined in banks. A rank is a plurality of banks in a first direction (column) and a channel is a plurality of banks in a second direction (row). A process for accessing the memory comprises several clock cycles required for row and column identification and a read or write operation. The bandwidth for the data transfer may comprise a row of many thousands of bits.
The conventional scheme for programming spin-torque MRAM is to apply a single current or voltage pulse to the memory cells to reverse the direction of their storage layer. The duration of the pulse is set by design requirements such as memory interface specifications. Generally, the write operation has to be completed in less than 50 ns. The write voltage amplitude is set to meet the memory write error rate (WER) and lifetime requirements. It has to be greater than a certain value Vw to assure that all bits are programmed reliably, with a write error rate below a defined value WER0. For megabit memories, WER0 is typically less than 10−8. The write voltage amplitude also has to be low enough to assure long-term device integrity. For magnetic tunnel junctions, elevated write voltage reduces the memory lifetime because of dielectric breakdown. In some cases, it is not possible to find a write voltage that meets the desired write error rate WER0 and the required lifetime. Known solutions to improve the write error rate are adding one or several layers of error correction or using multiple write pulses.
Memory devices commonly include some form of error correcting code (ECC) in the output logic circuitry. If a memory bit is not set correctly during the write operation, the ECC may be used to correct the data during a subsequent access. However, if the WER is too high, ECC will not be able to efficiently handle all the failing bits.
The write error rate or switching distribution of magnetic bits as a function of the applied voltage can be well described by an error function. That is why a common approach to set the write voltage for an assembly of bits is to increase it until the write error rate reaches the desired value WER0. Because of the stochastic nature of the magnetization reversal and the presence of defects in the memory elements, deviations from the ideal error function are commonly observed, resulting in an anomalously high write error rate and forcing the write voltage to be raised to meet WER0.
Solutions based on write patterns composed of multiple pulses have been proposed to improve the overall memory write error rate in the presence of bits with anomalous switching distributions. However, such solutions significantly increase the write duration and negatively impact the memory speed performance.
Accordingly, it is desirable to provide a method of improving the write error rate of a memory array without impacting its performance, such as speed and endurance. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.